View AD5100_4305146.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

System Management IC with Programmable Quad Voltage Monitoring and Supervisory Functions
AD5100
FEATURES
2 device-enabling outputs with 6 programmable monitoring inputs (see Table 1) Two 30 V monitoring inputs with shutdown control of external devices Programmable overvoltage, undervoltage, turn-on and turn-off thresholds, and shutdown timings Shutdown warning with fault detection Reset control of external devices 5 V and 7.96 V monitoring inputs with reset control of external devices Programmable reset thresholds and hold time eMOST-compatible inputs Diagnostic application using V2MON and V4MON Two supervisory functions Watchdog reset controller with programmable timeout and selectable floating input Manual reset control for external devices Digital interface and programmability I2C-compatible interface OTP1 for permanent threshold and timing settings OTP can be overwritten for dynamic adjustments Power-up by edge triggered signal Power-down over I2C bus Operating range Supply voltage: 6.0 V to 30 V Temperature range: -40C to +125C Shutdown current: 5 A max Operating current: 2 mA max High voltage input antimigration shielding pinouts
GENERAL DESCRIPTION
The AD5100 is a programmable system management IC that combines four channels of voltage monitoring and watchdog supervision. The AD5100 can be used to shut down external supplies, reset processors, or disable any other system electronics when the system malfunctions. The AD5100 can also be used to protect systems from improper device power-up sequencing. The AD5100, a robust watchdog reset controller, can monitor two 30 V inputs with shutdown and reset controls, one 2.3 V to 5.0 V input, and one 1.6 V to 7.96 V input. Most monitoring input thresholds and timing settings can be programmed on-the-fly or permanently set with the OTP memory feature. The AD5100 is versatile for system monitoring applications where critical microprocessor, DSP, and embedded systems operate under harsh conditions, such as automotive, industrial, or communications network environments. The AD5100 is available in a compact 16-lead QSOP package and can operate in an extended automotive temperature range from -40C to +125C. Table 1. AD5100 General Input and Output Information
Input V1MON V2MON V3MON V4MON WDI MR
1
Monitoring Range 1 6 V to 28.29 V 3 V to 24.75 V 2.32 V to 4.97 V 1.67 V to 7.96 V 0 V to 5 V 0 V to 5 V
Shutdown Control Yes Yes No No Yes No
Reset Control Yes Yes Yes Yes Yes Yes
Fault Detection Yes Yes Yes Yes No No
APPLICATIONS
Automotive systems Network equipment Computers, controllers, and embedded systems
With programmable threshold and programmable delay.
1
One-time programmable EPROM with unlimited adjustment before OTP execution.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
AD5100 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Functional Block Diagram .............................................................. 3 Specifications..................................................................................... 4 Electrical Specifications ............................................................... 4 Timing Specifications .................................................................. 7 Absolute Maximum Ratings............................................................ 8 ESD Caution .................................................................................. 8 Pin Configuration and Function Descriptions ............................. 9 One-Time Programmable (OTP) Options ............................. 10 Theory of Operation ...................................................................... 12 Monitoring Inputs .......................................................................... 13 V1MON ............................................................................................ 13 V2MON ............................................................................................ 14 V3MON ............................................................................................ 15 V4MON ............................................................................................ 16 Watchdog Input .......................................................................... 16 Manual Reset Input .................................................................... 18 Outputs ............................................................................................ 19 Shutdown Output, SHDN ......................................................... 19 Reset Output, RESET ................................................................. 19 Shutdown Warning, SHDNWARN .......................................... 20 V4OUT Output................................................................................ 20 Power Requirements ...................................................................... 21 Internal Power, VREG ................................................................... 21 VOTP............................................................................................... 21 Protection .................................................................................... 22 AD5100 Register Map .................................................................... 23 I2C Serial Interface.......................................................................... 27 Writing Data to AD5100 ........................................................... 28 Reading Data from AD5100 ..................................................... 28 Permanent Setting of AD5100 Registers (OTP Function) ... 29 Temporary Override of Default Settings ................................. 29 Applications Information .............................................................. 30 Car Battery and Infotainment System Supply Monitoring ... 30 Battery Monitoring with Fan Control ..................................... 33 Battery State of Charge Indicator and Shutdown Early Warning Monitoring .................................................................. 33 Rising Edge Triggered Wake-Up Mode ................................... 34 Outline Dimensions ....................................................................... 35 Ordering Guide .......................................................................... 35
REVISION HISTORY
9/08--Revision 0: Initial Version
Rev. 0 | Page 2 of 36
AD5100 FUNCTIONAL BLOCK DIAGRAM
V1MON (6V TO 30V)
AD5100
55k OV/UV
SHUTDOWN CONTROLLER
SHDN
V2MON (3V TO 30V)
640k
ON/OFF
SHDNWARN
V3MON (2.5V TO 5V)
130k
RESET GENERATOR
RESET
V4MON (0.9V TO 30V)
665k
V4OUT
MR WDI VOTP SDA SCL AD0 I2C CONTROLLER OTP FUSE ARRAY REGISTER MAP FD REGISTER FAULT DETECTION WDI DETECTION AND RESET GENERATOR
Figure 1.
Rev. 0 | Page 3 of 36
05692-001
AD5100 SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
6 V V1MON 30 V and 3 V V2MON 30 V, -40C TA +125C, unless otherwise noted. Table 2.
Parameter HIGH VOLTAGE MONITORING INPUTS V1MON Voltage Range Input Resistance OV, UV Threshold Tolerance (See Figure 7 and Table 6) Symbol Conditions Min Typ 1 Max Unit
V1MON RIN_V1MON OV, UV
TA = 25C TA = -40C to +85C TA = -40C to +125C
6 36 -1.6 -1.8 -2
55
30 70 +1.6 +1.8 +2
V k % % % % % % % s s V
Hysteresis Programmable Shutdown Hold Time Tolerance (See Figure 7 and Table 8) Programmable Shutdown Delay Tolerance (See Figure 7 and Table 8)
1.5 t1SD_HOLD t1SD_DELAY TA = 25C; does not apply to Code 0x7 TA = 25C; does not apply to Code 0x7 TA = -40C to +125C; does not apply to Code 0x7 Guaranteed by evaluation Minimum voltage on V2MON to ensure AD5100 VREG power-up 2.2 3 500 -2 -2.4 -2.5 1.5 t2SD_HOLD t2SD_DELAY TA = 25C; does not apply to Code 0x7 TA = 25C; does not apply to Code 0x07 TA = -40C to +125C; does not apply to Code 0x7 V2MON_OFF only -10 -10 -17 60 45 2.4 V1MON - 0.5 1.5 10 0.4 3 13.5 +10 +10 +17 30 760 +2 +2.4 +2.5 -10 -10 -17 60 45 +10 +10 +17
Fault Detection Delay Glitch Immune Time V2MON Input Voltage Voltage Range 2 Input Resistance On, Off Threshold Tolerance 3 (See Figure 7 and Table 6)
tFD_DELAY tGLITCH V2MON V2MON RIN_V2MON On, Off
640
TA = 25C TA = -40C to +85C TA = -40C to +125C
V k % % % % % % % s s V V V V mA
Hysteresis Turn-On Programmable SHDN Hold Time Tolerance (See Figure 7 and Table 8) Turn-Off Programmable SHDN Delay Time Tolerance (See Figure 7 and Table 8)
Fault Detection Delay Glitch Immune Time SHDN SHDN Output High SHDN Output Low SHDN Sink Current SHDNWARN (Open-Drain Output) SHDNWARN Inactive Leakage Current SHDNWARN Active
tFD_DELAY tGLITCH VOH VOL ISINK
VRAIL = VREG, ISOURCE = 40 A VRAIL = V1MON, ISOURCE = 600 A ISINK = 1.6 mA V1MON = 12 V, ISINK = 40 mA V1MON = 12 V, SHDN forced to 12 V
IOH_SHDNWARN VOL_SHDNWARN
0.9 ISINK = 3 mA 0.4
A V
Rev. 0 | Page 4 of 36
AD5100
Parameter LOW VOLTAGE MONITORING INPUTS V3MON, V4MON V3MON Voltage Range Input Resistance V3MON Threshold Tolerance (See Figure 10 and Table 6) Symbol Conditions Min Typ 1 Max Unit
V3MON RIN_V3MON V3MON
TA = 25C TA = -40C to +85C TA = -40C to +125C
2.0 110 -2.5 -2.75 -3
130
5.5 155 +2.5 +2.75 +3
V k % % % % V k % % % % % %
V3MON Hysteresis V4MON Voltage Range 4 Input Resistance V4MON Threshold Tolerance (See Figure 12 and Table 6)
V3_HYSTERESIS V4MON RIN_V4MON V4MON
1.2 0.9 580 -2.5 -2.75 -3 5 TA = 25C; does not apply to Code 0x6 and Code 0x7 TA = -40C to +125C; does not apply to Code 0x6 and Code 0x7 V3MON 4.38 V, ISOURCE = 120 A 2.7 V < V3MON 4.38 V, ISOURCE = 30 A 2.3 V < V3MON 2.7 V, ISOURCE = 20 A 1.8 V V3MON 2.3 V, ISOURCE = 8 A V3MON > 4.38 V, ISINK = 3.2 mA V3MON < 4.38 V, ISINK = 1.2 mA RESET = 0, V3MON = 5.5 V RESET = 0, V3MON = 3.6 V Open drain Applies to RESET disabled only TA = 25C TA = -40C to +125C -10 -17 50 tWD/50 1 0.3 x V3MON 0.7 x V3MON WDI = V3MON WDI = 0 160 -20 70 10 -10 -17 +10 +17 665 30 775 +2.5 +2.75 +3
TA = 25C TA = -40C to +85C TA = -40C to +125C
V4MON Hysteresis RESET RESET Hold Time Tolerance (See Figure 10, Figure 12, and Table 8)
V4_HYSTERESIS tRS_HOLD
V3MON/V4MON-to-RESET Delay RESET Output Voltage High
tRS_DELAY VOH
60 V3MON - 1.5 0.8 x V3MON 0.8 x V3MON 0.8 x V3MON 0.4 0.3 825 400 50 5.5
s V V V V V V A A s V s kHz
RESET Output Voltage Low RESET Output Short-Circuit Current 5 Glitch Immune Time V4OUT Maximum Output V4OUT Propagation Delay V4OUT Maximum Frequency WDI (WATCHDOG INPUT) WDI Programmable Timeout Tolerance (see Figure 13 and Table 8) WDI Pulse Width Watchdog Initiated RESET Pulse Width Watchdog Initiated SHDN WDI Input Voltage Low WDI Input Voltage High WDI Input Current
VOL ISOURCE tGLITCH V4OUT_MAX tV4OUT_DELAY fV4OUT
tWD
+10 +17
% % ns ms sec V V A A
tWDI tWDR tWD_SHDN VIL_WD VIH_WD
When no WDI When no WDI activity > 4 tWD
Rev. 0 | Page 5 of 36
AD5100
Parameter MR (MANUAL RESET) INPUT MR Input Voltage Low MR Input Voltage High Input Current MR Pulse Width MR Deglitching MR-to-RESET Delay MR Pull-Up Resistance (Internal to V3MON) RESET Hold Time Tolerance (see Figure 12 and Table 8) Symbol VIL_MR VIH_MR tMR tMR_GLITCH tMR_DELAY tRS_HOLD TA = 25C; does not apply to Code 0x6 and Code 0x7 TA = -40C to +125C; does not apply to Code 0x06 and Code 0x7 External RPULL-UP = 2.2 k External RPULL-UP = 2.2 k VRAIL = 2 V to 5.5 V IOL = 3 mA VIN = 0 V to 5.5 V Conditions Min Typ 1 Max 0.3 x V3MON 0.7 x V3MON 1 1 100 1 60 Unit V V A s ns s k % %
50 -10 -17
75 +10 +17
SERIAL INTERFACES Input Logic High (SCL, SDA) 6 Input Logic Low (SCL, SDA) Output Logic High (SDA) Output Logic Low (SDA) Input Current Input Capacitance POWER SUPPLY Supply Voltage Range Sleep Mode Supply Current Active Mode Supply Current
VIH VIL VOH VOL CI V1MON ISLEEP_V1MON IPOWER_V1MON
2.0 0 0.7 x VRAIL 0 5 6.0
5.5 0.8 0.4 1
V V V V A pF V A mA mA V V ms sec s V mA ms
V2MON = 0 V V2MON = 12 V V2MON edge triggered mode selected 2.2
30 5 2 2
Device Power-On Threshold Device Power-Up V2MON, Minimum Pulse Width Device Power-Down Delay OTP Supply Voltage 7 OTP Supply Current 8 OTP Settling Time 9
1 2
V2MON, IH V2MON, IL tV2MON_PW TVREG_OFF_DELAY VOTP IVOTP tS_OTP
0.4 4 V2MON < 0.4 V (normal mode) I2C-initiated power-down For OTP only For OTP only 2 10 5.5 84 12
Represent typical values at 25C, V1MON = 12 V, and V2MON = 12 V. Initial V2MON turn-on minimum remains as 2.2 V but the 3 V to 30 V specifications apply afterward. 3 Does not apply if V2MON is a digital signal. 4 V4MON threshold limits (see Table 6) are designed to primarily allow V4MON to monitor low voltage inputs. The V4MON input pin is capable of withstanding voltages up to 30 V. One application where this 30 V capability is useful is electronic media-oriented systems transport (eMOST) diagnostic circuits. 5 The RESET short-circuit current is the maximum pull-up current when RESET is driven low by a microprocessor bidirectional reset pin. 6 It is typical for the SCL and SDA to have resistors pulled up to V3MON. However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up resistors. 7 VOTP can be furnished by an external 5.5 V power supply, rather than an on-board power supply, when performing factory programming. A 10 F tantalum capacitor is required on VOTP during operation regardless of whether the OTP fuses are programmed. 8 The OTP supply source must be capable of supplying a minimum of 100 mA because some AD5100 parts require a current slightly greater than the typical value of 84 mA. 9 The OTP settling time occurs only once if the OTP function is used.
Rev. 0 | Page 6 of 36
AD5100
TIMING SPECIFICATIONS
Table 3.
Parameter I2C INTERFACE TIMING CHARACTERISTICS 1, 2 fSCL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
1 2
Description SCL clock frequency tBUF, bus free time between start and stop tHD;STA, hold time after (repeated) start condition; after this period, the first clock is generated tLOW, low period of SCL clock tHIGH, high period of SCL clock tSU;STA, setup time for start condition tHD;DAT, data hold time tSU;DAT, data setup time tF, fall time of both SDA and SCL signals tR, rise time of both SDA and SCL signals tSU;STO, setup time for stop condition
Min
Typ
Max 400
Unit kHz s s s s s s s s s s
1.3 0.6 1.3 0.6 0.6 0.1 0.3 0.3 0.6
50 0.9
Guaranteed by design and not subject to production test. See Figure 2.
t2
t8
SCL
t6
t9
t2
t3 t8 t9
t4
t7
t5
t10
SDA
t1
P S S P
Figure 2. Digital Interface Timing Diagram
Rev. 0 | Page 7 of 36
05692-002
AD5100 ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter V1MON to GND V2MON to GND V3MON to GND V4MON to GND VOTP to GND Digital Input Voltage to GND (MR, WDI, SCL, SDA, AD0) Digital Output Voltage to GND (RESET, V4OUT, SHDNWARN) Digital Output Voltage to GND (SHDN) Operating Temperature Range Storage Temperature Range ESD Rating (HBM) Maximum Junction Temperature (TJmax) Power Dissipation 1 Thermal Impedance 3 JA Junction-to-Ambient JC Junction-to-Case IR Reflow Soldering (RoHS-Compliant Package) Peak Temperature Time at Peak Temperature Ramp-Up Rate Ramp-Down Rate Time from 25C to Peak Temperature
1 2
Rating -0.3 V, +33 V -0.3 V, +33 V -0.3 V, +7 V -0.3 V, +33 V -0.3 V, +7 V 0 V, +7 V 0 V, +7 V 0 V, +33 V -40C to +125C -65C to +150C 3.5 kV 150C (TJmax - TA 2 )/JA 105.44C/W 38.8C/W 260C (+0C) 20 sec to 40 sec 3C/sec max -6C/sec max 8 minutes max
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Values relate to the package being used on a 4-layer board. TA = ambient temperature. 3 Junction-to-case resistance is applicable to components featuring a preferential flow direction, for example, components mounted on a heat sink. Junction-to-ambient resistance is more useful for air-cooled PCB-mounted components.
Rev. 0 | Page 8 of 36
AD5100 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V1MON 1 GND 2 VOTP 3 V3MON 4
16 15 14
V2MON GND/NC V4MON
AD0 TOP VIEW MR 5 (Not to Scale) 12 SHDN
13 11 10 9
AD5100
WDI 6 SCL 7 SDA 8
SHDNWARN V4OUT
05692-003
RESET
NC = NO CONNECT
Figure 3. Pin Configuration
Table 5. AD5100 Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic V1MON GND VOTP V3MON MR WDI SCL SDA RESET V4OUT SHDNWARN SHDN AD0 V4MON GND/NC V2MON Description High Voltage Monitoring Input. AD5100 internal supply is derived from V1MON. There must be a 10 F electrolytic capacitor between this pin and GND, placed as close as possible to the V1MON pin. Ground. One-Time Programmable Supply Voltage for EPROM. A 10 F decoupling capacitor (low ESR) to GND is required when not fuse programming. Low Voltage Monitoring Input. Manual Reset Input. Active low. Watchdog Input. I2C Serial Input Register Clock. Open-drain input. If it is driven directly from a logic driver without the pull-up resistor, ensure that the VIH minimum is 3.3 V. I2C Serial Data Input/Output. Open-drain input/output. If it is driven directly from a logic driver without the pullup resistor, ensure that the VIH minimum is 3.3 V. Reset. Push-pull output with rail voltage of V3MON. Open-Drain Output. Triggered by V4MON. Shutdown Warning. Active low, open-drain output. Shutdown Output. Push-pull output with selectable rail voltage of V1MON or VREG, the AD5100 internal power (30 V maximum). I2C Slave Address Configuration. If tied high, this pin can only be tied to 3.3 V maximum. Low Voltage Monitoring Input. Capable of withstanding 30 V. Ground/No Connect. Can be grounded or left floating but do not connect to any other potentials. High Voltage Monitoring Input. It is also the internal supply voltage enabling input.
GND
1 2 3 4 5 6 7 8 16 15 14
AD5100
TOP VIEW (Not to Scale) 12
11
05692-004
13
10 9
Figure 4. Recommended PCB Layout for Shielded High Voltage Inputs
Rev. 0 | Page 9 of 36
AD5100
ONE-TIME PROGRAMMABLE (OTP) OPTIONS
All values are typical ratings; see Table 2 for tolerances. Table 6. Available Programmable Thresholds at TA = 25C
V1MON OV Threshold 7.92 V 9.00 V 9.90 V 11.00 V 12.00 V 13.20 V 14.14 V 15.23 V 15.84 V 17.22 V 18.00 V 1 18.86 V 19.80 V 22.00 V 24.75 V 28.29 V
1
V1MON UV Threshold 6.00 V 6.49 V 6.95 V 7.47 V 7.92 V 8.43 V1 9.00 V 9.43 V 9.90 V 10.42 V 11.00 V 11.65 V 12.00 V 12.38 V 13.20 V 13.66 V
V2MON On Threshold 3.00 V 3.5 V 4.00 V 4.77 V 6.00 V 6.49 V 6.95 V 7.47 V1 7.92 V 8.43 V 9.00 V 9.43 V 9.90 V 15.23 V 19.80 V 24.75 V
V2MON Off Threshold 3.00 V 3.5 V 4.00 V 4.77 V 6.00 V 6.49 V 6.95 V1 7.47 V 7.92 V 8.43 V 9.00 V 9.43 V 9.90 V 15.23 V 19.80 V Rising edge triggered wake-up mode
V3MON Threshold 2.32 V 2.64 V 2.93 V1 3.10 V 4.36 V 4.65 V 4.75 V 4.97 V Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
V4MON Threshold 1.67 V 2.31 V 3.05 V 4.62 V 6.51 V 7.16 V 7.54 V1 7.96 V Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Default. V1MON_OV must be > V1MON_UV. V2MON_OFF is ignored if > V2MON_ON but V2MON_OFF cannot be = V2MON_ON.
Table 7. Look-Up Table of Programming Code vs. Typical Thresholds Shown in Table 6
Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
1
V1MON OV Threshold 18.00 V 1 18.86 V 15.84 V 17.22 V 24.75 V 28.29 V 19.80 V 22.00 V 9.90 V 11.00 V 7.92 V 9.00 V 14.14 V 15.23 V 12.00 V 13.20 V
V1MON UV Threshold 8.43 V1 7.92 V 9.43 V 9.00 V 6.49 V 6.00 V 7.47 V 6.95 V 12.38 V 12.00 V 13.66 V 13.20 V 10.42 V 9.90 V 11.65 V 11.00 V
V2MON On Threshold 7.47 V 1 6.95 V 6.49 V 6.00 V 4.77 V 4.00 V 3.50 V 3.00 V 24.75 V 19.80 V 15.23 V 9.90 V 9.43 V 9.00 V 8.43 V 7.92 V
V2MON Off Threshold 6.95 V1 7.47 V 6.00 V 6.49 V 4.00 V 4.77 V 3.00 V 3.50 V 19.80 V Rising edge triggered wake-up mode 9.90 V 15.23 V 9.00 V 9.43 V 7.92 V 8.43 V
V3MON Threshold 2.93 V1 4.65 V 4.75 V 4.97 V 2.32 V 2.64 V 4.36 V 3.10 V Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
V4MON Threshold 7.54 V1 1.67 V 2.31 V 3.05 V 4.62 V 6.51 V 7.16 V 7.96 V Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Default.
Rev. 0 | Page 10 of 36
AD5100
Table 8. Available Programmable Hold Time and Delay
t1SD_HOLD 0.07 ms 20 ms 40 ms 60 ms 80 ms 100 ms 150 ms 200 ms1
1
t1SD_DELAY 0.07 ms 50 ms 100 ms 200 ms 400 ms 800 ms 1000 ms 1200 ms1
t2SD_HOLD 0.07 ms 10 ms 1 20 ms 30 ms 40 ms 50 ms 100 ms 200 ms
t2SD_DELAY 0.07 ms 50 ms 100 ms1 200 ms 400 ms 800 ms 1000 ms 1200 ms
tRS_HOLD 0.1 ms 1 ms 15 ms 30 ms 50 ms 100 ms 150 ms 200 ms1
tWD 100 ms 250 ms 500 ms 750 ms 1000 ms 1250 ms 1500 ms1 2000 ms
Default.
Table 9. Look-Up Table of Programming Code vs. Typical Timings Shown in Table 8
Code 000 001 010 011 100 101 110 111
1
t1SD_HOLD 200 ms 1 150 ms 100 ms 80 ms 60 ms 40 ms 20 ms 0.07 ms
t1SD_DELAY 1200 ms1 1000 ms 800 ms 400 ms 200 ms 100 ms 50 ms 0.07 ms
t2SD_HOLD 10 ms1 20 ms 30 ms 40 ms 50 ms 100 ms 200 ms 0.07 ms
t2SD_DELAY 100 ms1 50 ms 200 ms 400 ms 800 ms 1000 ms 1200 ms 0.07 ms
tRS_HOLD 200 ms1 150 ms 100 ms 50 ms 30 ms 15 ms 1 ms 0.1 ms
tWD 1500 ms1 2000 ms 1250 ms 1000 ms 750 ms 500 ms 250 ms 100 ms
Default.
Rev. 0 | Page 11 of 36
AD5100 THEORY OF OPERATION
The AD5100 is a programmable system management IC that has four channels of monitoring inputs. Three inputs have high voltage (30 V) capability. For example, if the AD5100 is used in an automotive application, V1MON (Monitoring Input 1) can be connected to the battery and the V2MON can be connected to the ignition switch, a rising edge trigger wake-up signal, or the media-oriented systems transport (MOST) wake-up signal (V4MON is connected to V2MON for MOST applications). Two other inputs, V3MON and V4MON, are designed for low voltage monitoring, with programmable thresholds from 2.93 V to 7.96 V. The two high voltage monitoring inputs control the shutdown signal, SHDN and reset signal, RESET, while the two low voltage monitoring inputs control the reset signal, RESET. SHDN and RESET are both disabling signals for external devices. The differences between these two outputs are in output level and driving capabilities, as described in the Outputs section. The WDI (watchdog) and MR (manual reset) inputs also control the RESET output, for use with an external digital processor. Figure 5 shows the general flow chart and Table 10 summarizes the AD5100 functions and features.
MR = 1 V1MON > UV YES V1MON < OV YES V2MON LEVEL SENSITIVE SELECTED YES V2MON > ON YES V2MON > OFF YES SHDN = 1 NO SHDN = 0 NO SHDN = 0 V3MON > THRESHOLD YES USING V4OUT FOR PWM YES V4MON > THRESHOLD V4OUT = 1 YES NO NO SHDN = 0* (V2MON RISING EDGE SENSITIVE SELECTED) NO SHDN = 0* YES
NO
RESET = 0
NO FLOATING WDI DISABLED YES NO (ADVANCE WDI SELECTED) STANDARD WDI SELECTED YES VALID WDI YES NO RESET = 0 VALID WDI YES
FLOATING WDI YES RESET = 0
NO
NO
RESET = 0 SHDN = 0
NO
RESET = 0
NO
V4MON > THRESHOLD YES
NO
RESET = 0
NO
V4OUT = 0
Figure 5. General Flow Chart
Table 10. AD5100 Functions and Features
Input V1MON V2MON Monitoring Range 6 V to 28.29 V 3 V to 24.75 V Shutdown Control Yes Yes Reset Control Yes Yes Fault Detection Yes Yes Functions and Features Overvoltage/undervoltage thresholds On/off voltage thresholds; pseudo rising edge triggered, wake-up selectable; MOST wake-up signal (V2MON connected to V4MON) If Not Used Does not apply Connect to V1MON, minimum input 6 V Connect to VOTP and set threshold to minimum Connect to GND Leave floating Leave floating
V3MON
2.32 V to 4.97 V
No
Yes
Yes
V4MON WDI MR
1.67 V to 7.96 V 0 V to 5 V 0 V to 5 V
No Yes Yes
Yes Yes Yes
Yes No No
Additional output Standard, advance, or floating; watchdog selectable Highest priority on RESET over other inputs
Rev. 0 | Page 12 of 36
05692-005
CONTINUE MONITORING
DEFAULT PATHS * SEE TABLE 11 RESET CONFIGURATION REGISTER: IF [0] = 0, THEN SHDN = 0 AND RESET = 0 IF [0] = 1, THEN SHDN = 0 AND RESET = 1
AD5100 MONITORING INPUTS
V1MON
V1MON is a high voltage monitoring input that controls the SHDN and RESET functions of the external devices. In addition, it provides a shutdown warning to the system. V1MON monitors inputs from 6 V to 30 V. The V1MON pin is monitored by two comparators, one for overvoltage and one for undervoltage detection. Both are designed with 1.5% hysteresis. When the V1MON input goes above the programmed overvoltage (OV) threshold, the comparator becomes active immediately, indicating that an OV condition has occurred. Due to hysteresis, the V1MON input must be brought below the programmed OV threshold by 1.5% before the comparator becomes inactive, indicating that the OV condition has gone away (see Figure 6).
V1MON_OV HYSTERESIS
shutdown delay (t1SD_DELAY). The shutdown hold time means that the SHDN signal is held low for t1SD_HOLD after V1MON returns within its UV and OV thresholds. The shutdown delay means that the SHDN signal activation is delayed until the programmed t1SD_DELAY has elapsed. SHDN activates once the voltage on V1MON is outside the OV or UV threshold for a time longer than tGLITCH. RESET follows SHDN delay and hold timings when triggered by VIMON. The OV threshold chosen must be greater than the UV threshold. When the shutdown is triggered, either because the input has reached the OV or UV threshold, such fault conditions are temporarily recorded in the fault detection register. The SHDNWARN output transitions low for signaling before the shutdown output, SHDN, activates. The timing of the SHDN output is dependent on how long the shutdownprogrammed delay (t1SD_DELAY ) is set relative to the SHDNWARN propagation delay (tFD_DELAY). This feature attempts to allow the system to finish any critical housekeeping tasks before shutting down the external device. The V1MON, shutdown, and shutdown warning timing diagrams are shown in Figure 7. The ranges of OV and UV thresholds are shown in Table 6, and the programming codes for the selected thresholds are found in Table 7. The defaulted OV threshold is 18.00 V and, for UV threshold, it is 8.43 V. Similarly, the ranges of shutdown hold and delay times are shown in Table 8, and the programming codes for the selected timings are shown in Table 9. The default shutdown hold time is 200 ms; for shutdown delay time, it is 1200 ms. V1MON exhibits typical input resistance of 55 k that users should take into account for loading effect. The voltage at V1MON provides the power for the AD5100, but a valid signal on V2MON must be present before the internal power rail, VREG, starts operation. Details are explained in the Power Requirements section.
V1MON
V1MON_UV
HYSTERESIS OV COMPARATOR ACTIVE OV COMPARATOR INACTIVE
05692-007
UV UV COMPARATOR COMPARATOR ACTIVE INACTIVE
Figure 6. V1MON Hysteresis
When the V1MON input drops below the programmed undervoltage (UV) threshold, the comparator becomes active immediately, indicating that a UV condition has occurred. Similarly, due to hysteresis, the V1MON input must be brought above the programmed UV threshold by 1.5% before the comparator becomes inactive, indicating that the UV condition has gone away. Both V1MON comparators are used (in conjunction with hold and delay timers) to control the SHDN and RESET pins. V1MON has a 16-level programmable OV threshold (Register 0x01) and UV threshold (Register 0x02) with an 8-step 0.07 ms to 200 ms shutdown hold time (t1SD_HOLD) and 0.07 ms to 1200 ms
Rev. 0 | Page 13 of 36
AD5100
tGLITCH
V1MON V1MON_UV* V1MON_OV*
tGLITCH
V2MON_ON* V2MON V2MON_OFF*
tMIN# t1SD_DELAY* t2SD_HOLD*
SHDN AND RESET
t1SD_DELAY* t1SD_HOLD* t2SD_DELAY*
t2SD_HOLD*
t2SD_DELAY*
t1SD_HOLD*
tFD_DELAY
tFD_DELAY
tFD_DELAY
tFD_DELAY
SHDNWARN
NOTES 1. * = PROGRAMMABLE. 2. # = THE DURATION OF THE tMIN MUST BE SHORTER THAN tVREG_OFF_DELAY OR ELSE THE AD5100 WILL BE POWERED OFF.
Figure 7. V1MON and V2MON Shutdown Timing Diagrams in Level-Sensitive Mode (Note that RESET Follows SHDN)
V2MON
V2MON is a high voltage monitoring input that controls the SHDN and RESET functions of the external devices. V2MON monitors inputs from 3 V to 30 V. It has a 16-level programmable turn-on and turn-off (on, off) hysteresis thresholds (Register 0x03 and Register 0x04), with an 8-step 0.07 ms to 200 ms shutdown hold time (t2SD_HOLD) and 0.07 ms to 1200 ms shutdown delay (t2SD_DELAY). The V2MON pin is monitored by two comparators, one for turnon and one for turn-off detection, in the level-sensitive powerup mode. Both are designed with 1.5% hysteresis. Only the turn-on monitoring comparator is used if the rising edge triggered wake-up mode is selected. When the V2MON input goes above the programmed V2MON on threshold, the comparator becomes active immediately, indicating that an on condition has occurred. Due to hysteresis, the V2MON input must be brought below the programmed threshold by 1.5% before the comparator becomes inactive, indicating that the on condition has gone away (see Figure 8). When the V2MON input drops below the programmed threshold, the comparator becomes active immediately, indicating that a V2MON off condition has occurred. Similarly, due to hysteresis, the V2MON input must be brought above the programmed threshold by 1.5% before the comparator becomes inactive, indicating that the off condition has gone away.
V2MON_ON HYSTERESIS
V2MON
V2MON_OFF
ON COMPARATOR ACTIVE
ON COMPARATOR INACTIVE
05692-008
OFF OFF COMPARATOR COMPARATOR ACTIVE INACTIVE
Figure 8. V2MON Hysteresis
By default, V2MON is level sensitive and the on and off thresholds are both monitored. The on threshold chosen must be greater than the off threshold. When the SHDN output is activated by the input reaching the V2MON_OFF threshold, such fault condition is temporarily recorded in the fault detection register. The SHDNWARN output transitions low for signaling before the shutdown output, SHDN, activates. The timing of the SHDN output is dependent on how long the shutdown programmed delay (t2SD_DELAY) is set relative to the SHDNWARN propagation delay (tFD_DELAY ). This feature allows the system to finish any critical housekeeping tasks before shutting down the external device. SHDN activates once the voltage on V2MON is outside the threshold for a time longer than tGLITCH. RESET follows SHDN delay and hold timings when triggered by V2MON. The V2MON, shutdown, and shutdown warning timing diagrams are shown in Figure 7.
Rev. 0 | Page 14 of 36
05692-006
HYSTERESIS
AD5100
The ranges of on and off thresholds are shown in Table 6 and the programming codes for the selected-thresholds are found in Table 7. The default on threshold is 7.47 V and off threshold is 6.95 V. Similarly, the ranges of shutdown hold and delay times are shown in Table 8, and the programming codes of the selected timings are found in Table 9. The default shutdown hold time is 10 ms and the delay time is 100 ms. V2MON_OFF is ignored if V2MON_OFF is greater than V2MON_ON but V2MON_OFF cannot equal V2MON_ON. If V2MON is selected with rising edge triggered wake-up mode, only the on threshold is monitored and the off threshold is ignored. V2MON is put into rising edge triggered mode by setting V2MON off threshold, Register 0x04[3:0] to 1001 The voltage at V1MON provides the power for the AD5100, but a valid signal on V2MON must be present before the internal VREG starts operating. Details are explained in the Power Requirements section. V2MON exhibits typical input resistance of 640 k that users should take into account for loading effect.
V3MON V3MON_UV HYSTERESIS
Figure 9. V3MON Hysteresis
The V3MON comparator is used (in conjunction with a hold timer) to control the RESET pin. V3MON monitors inputs from 2.0 V to 5.5 V. It has an 8-step programmable reset threshold (Register 0x05) with an 8-step 0.1 ms to 200 ms reset hold time (tRS_HOLD). The reset hold time means that the RESET output remains activate when V3MON goes above its UV threshold, until tRS_HOLD has elapsed. This allows the reset of an external device to be held until the programmed time is reached. The V3MON and RESET timing diagrams are shown in Figure 10. The range of thresholds is shown in Table 6 and the programming code for the selected threshold is found in Table 7. The default monitoring threshold is 2.93 V. The range of reset hold times is shown in Table 8 and the programming code of the selected timing is found in Table 9. The default RESET hold time is 200 ms. V3MON exhibits typical input resistance of 130 k that users should take into account for loading effect. The MR input has an internal resistor pull-up toV3MON. The RESET output is push-pull, between V3MON and GND.
V3MON
V3MON is a low voltage monitoring input that controls the RESET function of an external device. The V3MON pin is monitored by a comparator to detect an undervoltage condition. It is designed with 1.5% hysteresis. When the V3MON input drops below the programmed UV threshold, the comparator becomes active immediately, indicating that a UV condition has occurred. Due to hysteresis, the V3MON input must be brought above the programmed UV threshold by 1.5% before the comparator becomes inactive, indicating that the UV condition has gone away (see Figure 9).
tGLITCH
V3MON V3MON
tRS_HOLD* tRS_DELAY
tRS_HOLD* tRS_DELAY
RESET
NOTES 1. * = PROGRAMMABLE
Figure 10. V3MON, RESET Timing Diagrams
Rev. 0 | Page 15 of 36
05692-009
05692-010
UV COMPARATOR INACTIVE
UV COMPARATOR INACTIVE
AD5100
V4MON
V4MON is a low voltage monitoring input that controls the RESET function of an external device or provides a comparator output, V4OUT. The V4MON pin is monitored by a comparator to detect an undervoltage condition. It is designed with 5% hysteresis. When the V4MON input drops below the programmed UV threshold, the comparator becomes active immediately, indicating that a UV condition has occurred. Due to hysteresis, the V4MON input must be brought above the programmed UV threshold by 5% before the comparator becomes inactive, indicating that the UV condition has gone away (see Figure 11).
V4MON
7.96 V, with an 8-step 0.1 ms to 200 ms reset hold time (tRS_HOLD). The V4MON, RESET, and V4OUT timing diagrams are shown in Figure 12. The range of thresholds is shown in Table 6, and the programming code for the selected threshold is found in Table 8. The default monitoring threshold is 7.54 V. Similarly, the range of reset hold time is shown in Table 8, and the programming code of the selected timing is found in Table 9. V4MON exhibits typical input resistance of 665 k that users should take into account for loading effect.
WATCHDOG INPUT
The watchdog input (WDI) circuit attempts to reset the system to a known good state if a software or hardware glitch renders the system processor inactive for a duration that is longer than the timeout period. The timeout period, tWD, is programmable in eight steps from 100 ms to 2000 ms. The watchdog circuit is independent of any CPU clock that the watchdog is monitoring. The range of watchdog timeout is shown in Table 8, and the programming code of the selected timeout is found in Table 9. The default timeout is 1500 ms. The watchdog is disabled during power-up. WDI starts monitoring once RESET is high. The AD5100 provides a standard or advanced watchdog monitoring function. Register 0x0F[3] sets the watchdog function to either standard or advanced mode. * * Register 0x0F[3] = 0: standard watchdog mode Register 0x0F[3[ = 1: advanced watchdog mode
V4MON_UV
HYSTERESIS
Figure 11. V4MON Hysteresis
The V4MON comparator is used to control the V4OUT pin and (in conjunction with a hold timer) to control the RESET pin. To configure V4MON to control the RESET pin, set Register 0x0D[3] to 0. Setting this bit to 1 prevents V4MON from causing RESET to activate. V4MON input voltage range is up to 30 V. It has an 8-step programmable reset threshold (Register 0x06) from 1.67 V to
tGLITCH
V4MON V4MON
tRS_HOLD* tRS_DELAY
05692-012
UV COMPARATOR INACTIVE
UV COMPARATOR INACTIVE
tRS_HOLD* tRS_DELAY
RESET
V4OUT
NOTES 1. * = PROGRAMMABLE. 2. MOST APPLICATIONS USING V4OUT REQUIRE DISABLING OF V4MON TRIGGERED RESET.
Figure 12. V4MON , RESET, and V4OUT Timing Diagrams
Rev. 0 | Page 16 of 36
05692-011
AD5100
Standard Watchdog Mode
In the default standard watchdog mode, if WDI remains either high or low for longer than the timeout period, tWD, a RESET pulse is generated in an attempt to allow the system processor to re-establish the WDI signal. The RESET pulses continue indefinitely until a valid watchdog signal, a rising or falling edge signal at the WDI, is received. The internal watchdog timer clears whenever a reset is asserted. The standard WDI and RESET timing diagrams are shown in Figure 13.
Advanced Watchdog Mode
The AD5100 can be programmed into an advanced watchdog mode. In this mode, if WDI remains either high or low for longer than the timeout period, tWD, a RESET pulse is generated, as per standard mode. However, if the WDI input remains inactive after three such RESET pulses, concurrent with the fourth RESET pulse, SHDN is also asserted. SHDN is released after 1 second. These actions repeat indefinitely (unless action is taken by the user), if the processor is not responding. The advanced WDI and RESET timing diagrams are shown in Figure 14.
tWDI
WDI
tWD tWDR
tWD tWDR
RESET
RESET PULSE
CONTINUOUS PULSES UNTIL WATCHDOG AWAKES
Figure 13. Standard Watchdog--Pulsing Reset Until Watchdog Awakes
tWDI
WDI
tWD tWDR
tWD tWDI
RESET 1 RESET PULSE 3 RESET PULSES
tWD_SHDN
SHUTDOWN AT 4TH RESET PULSE RELEASE AFTER 1s
SHDN
Figure 14. Advanced Watchdog--SHDN Asserted After Three Trials of Resetting the Watchdog (SHDN Released After 1 Second and the Cycle Repeats)
Rev. 0 | Page 17 of 36
05692-014
05692-013
tWDR = WATCHDOG-INITIATED RESET PULSE WIDTH tWDI = WATCHDOG PULSE WIDTH tWD = WATCHDOG PROGRAMMABLE TIME
AD5100
Floating WDI Input
If the WDI pin is floating, the watchdog function is disabled by default. However, floating watchdog can be enabled in the RESET configuration register such that a broken WDI connection or any unusual condition that makes WDI float triggers the reset. * * Register 0x0D[3] = 0: floating WDI input activates RESET Register 0x0D[3] = 1: floating WDI input does not activate RESET
MANUAL RESET INPUT
Manual reset (MR) is an active low input to the AD5100 and has an internal pull-up resistor to V3MON. If the input signal on the MR pin goes low, RESET is activated. MR can be driven from a CMOS logic signal. The MR and RESET timing diagrams are shown in Figure 15. Note that RESET is activated after tMR_DELAY and is held for tRS_HOLD after the MR signal has gone high again. MR has the highest priority in triggering the RESET over any other monitoring inputs.
MR < tMR_GLITCH
Enabling or disabling the floating WDI feature can be changed dynamically, provided that the OTP fuse of the RESET configuration register is not blown or that the OTP overridden function is selected.
tMR tMR_DELAY tRS_HOLD*
RESET * = PROGRAMMABLE
05692-015
Figure 15. Manual Reset (MR) Timing Diagram
Rev. 0 | Page 18 of 36
AD5100 OUTPUTS
SHUTDOWN OUTPUT, SHDN
The shutdown output, SHDN, is triggered by V1MON or V2MON over- or underthreshold values, or as the result of a failed watchdog input. SHDN can also be asserted low at any time by writing to certain registers on the AD5100. The shutdown generator asserts a logic low SHDN signal based on the following conditions: * * * During power-up When V1MON goes over or under the threshold (see Figure 7) When V2MON is below the turn-on threshold during the rising edge or the turn-off threshold during the falling edge in level-sensitive mode (see Figure 7) When the external monitoring processor cannot issue the necessary WDI signal and advanced WDI mode is selected (see Figure 10 and Figure 9) I2C(R) programmed shutdown have formed across the SHDN pin and the battery terminal (V1MON). The dendrite is blown immediately because M2a is designed with adequate current sinking capability and remains in the on position to offer such protection. In another situation, if the SHDN pin is hard-shorted to the 12 V battery, the shortcircuit detector opens SW2 and limits the current by the high impedance M2b.
V1MON # SW3 VREG
#* SW1
M1
LEVEL SHIFTER
M3
SHDN R1 * SW2 LOW-Z HIGH-Z M2A M2B
*
*
* *
Register 0x18[4] = 0: enable software control of SHDN Register 0x18[4] = 1: disable software control of SHDN
Figure 16. Shutdown Output
Once the feature is enabled, control of SHDN is achieved by writing to Register 0x16[2]. * * Register 0x16[2] = 0: SHDN output not controlled by software Register 0x16[2] = 1: SHDN output is pulled low
RESET OUTPUT, RESET
The reset output, RESET, is triggered by V3MON or V4MON underthreshold values. RESET activation can also be the result of the processor not generating the proper watchdog signal, if MR input is triggered, or if SHDN is activated. The reset generator asserts the RESET signal based on the following conditions: * * * * During power-up When V3MON drops below the threshold (see Figure 10) When V4MON drops below the threshold (see Figure 12) When SHDN output is asserted (see Figure 7 and Figure 14); RESET follows SHDN hold and delay timings if triggered by the SHDN output When the external monitoring processor cannot issue the necessary WDI signal (see Figure 13 and Figure 14) When MR is asserted (see Figure 15)
The SHDN signal is released after the programmable hold time, tSD_HOLD. The SHDN output is push-pull configured with an I2Cselectable rail voltage of either V1MON in default or internal VREG. Register 0x0E controls the voltage rail for SHDN. * * Register 0x0E[3] = 0: SHDN uses V1MON rail Register 0x0E[3] =1: SHDN uses VREG rail
Figure 16 shows the SHDN output configuration. Pull-down Resistor R1 ensures that SHDN is pulled to ground when the AD5100 is not powered. When AD5100 is powered, M2a and M2b are both on. M2a has relatively lower impedance than M2b and R1 so the SHDN remains low at shutdown. When the AD5100 settles, SW1 is turned on. M1 is stronger than M2a so SHDN is pulled to the rail, which takes AD5100 out of the shutdown mode. In some applications, the AD5100 may monitor and control power regulators where the input and enable pins are next to each other in a fine pitch. This may pose reliability concerns under some abnormal conditions. To prevent errors from happening, the AD5100 shutdown output features smart-load detection to ensure that the shutdown responds. For example, if the car battery has not started for a long time, a resistive dendrite may
* *
RESET is active low by default, but can be configured for active high operation. Register 0x0D[1] controls the activation polarity of RESET. * * Register 0x0D[1] = 0: RESET is active low Register 0x0D[1] = 1: RESET is active high
Rev. 0 | Page 19 of 36
05692-016
To activate SHDN by writing to the part, the user must first enable this feature by writing to Register 0x18[4].
NOTES 1. # = I2C SELECTABLE 2. * = DEFAULT
SHORT-CIRCUIT DETECT
AD5100
The RESET signal is asserted and maintained except when it is triggered by the WDI, which is described in the Watchdog Input section. The RESET signal is released after the programmable hold time, tRS_HOLD. As shown in Figure 17, the RESET output is push-pull configured with the rail voltage of V3MON.
V3MON
the voltage at V2MON falls below the threshold, SHDNWARN outputs a Logic 0. If the processor sees a logic low on this pin, the processor may issue an I2C read command to identify the cause of failure reported in the fault detect/status register, at Address 0x19. The processor may store the information in external EEPROM as a record of failure history.
V4OUT OUTPUT
V4OUT is an open-drain output triggered by V4MON with a minimum propagation delay, tV4OUT_DELAY. V4OUT can be used as a PWM control over an external device or used as a monitoring signal.
RESET
M1
M2
05692-017
Most applications using V4OUT require disabling of the V4MON triggered reset function. This function is disabled by writing to Register 0x0D[2]. * * Register 0x0D[2] = 0: enables V4MON under threshold to activate RESET Register 0x0D[2] = 1: prevents V4MON under threshold from activating RESET
Figure 17. Reset Output
SHUTDOWN WARNING, SHDNWARN
An early shutdown warning is available for the system processor to identify the source of failure and take appropriate action before shutting down the external devices. Whenever the voltage at V1MON is detected as overvoltage or undervoltage, or
Rev. 0 | Page 20 of 36
AD5100 POWER REQUIREMENTS
INTERNAL POWER, VREG
The AD5100 internal power, VREG, is derived from V1MON and becomes active when V2MON reaches 2.2 V. V2MON is used to turn AD5100 on and off with a different behavior depending on the V2MON monitoring mode selection. By default, the AD5100 turns on when the voltage at V2MON rises above the logic threshold, V2MON_ON. When V2MON falls below the logic threshold, V2MON_OFF, AD5100 turns off 2 seconds after SHDN is deasserted. Note that AD5100 requires 5 s to start up and that V1MON must be applied before V2MON. Extension of the AD5100 turn-off allows the system to complete any housekeeping tasks before the system is powered off. Figure 19 shows the default V2MON and VREG waveforms.
VOTP
A 5.5 V supply voltage is needed only during OTP fuse programming. This voltage should be provided by an external source during factory programming and should have 5.5 V/100 mA driving capability. The OTP programming takes a maximum of 12 ms for each register. VOTP is not required for normal operation. The VOTP has dual functions; it is used for programming the nonvolatile memory fuse arrays, as well as serving as a compensation network for internal power stability. As a result, a bypass capacitor must be connected at the VOTP pin at all times. A low ESR 10 F tantalum capacitor is recommended. AD5100 achieves the OTP function through blowing internal fuses. Users should always apply the 5.5 V one-time programmable voltage at the first fuse programming attempt. Failure to comply with this requirement may lead to a change in the fuse structures, rendering programming inoperable. Poor PCB layout introduces parasitic inductance that may affect the fuse programming voltage. Therefore, it is mandatory that a 10 F tantalum capacitor be placed as close as possible to the VOTP pin. The value and the type of C2 are important. It should provide both a fast response and large supply current handling with minimum supply droop during programming (see Figure 18).
6V TO 30V V1MON
Rising Edge Triggered Wake-Up Mode
If rising edge triggered wake-up V2MON mode is selected instead, the AD5100 does not turn off when V2MON returns to a logic low. To configure the part into rising edge triggered mode, set the V2MON off threshold register, Register 0x04[3:1], to 1001. In this mode, once the part is powered on, it can only be powered down by an I2C power-down instruction or by removing the supply on the V1MON pin. To power down the part over the I2C bus while in rising edge triggered mode, the user must first ensure that the software power down feature is enabled. * * Register 0x18[3] = 0: enable software power-down feature Register 0x18[3] =1: disable software power-down feature
AD5100
3V TO 30V V2MON
C2 10F
* *
Register 0x17[0] = 0: AD5100 not in software power-down Register 0x17[0] = 1: power down AD5100
tGLITCH
Figure 18. Power Supply Requirement
This feature is for applications that use a wake-up signal.
V2MON_ON* V2MON V2MON,IH V2MON_OFF*
V2MON_ON* V2MON_OFF*
t2SD_HOLD*
t2SD_DELAY*
t2SD_HOLD*
t2SD_DELAY* t2SD_DELAY*
SHDN
tVREG_ON_DELAY
tVREG_OFF_DELAY
VREG
tVREG_OFF_DELAY
Figure 19. Internal Power VREG vs. V2MON Timing Diagrams (Default)
Rev. 0 | Page 21 of 36
05692-018
NOTES 1. 6V < V1MON < 30V 2. * = PROGRAMMABLE
05692-019
The user must then write to Register 0x17[0], to actually power down the AD5100.
APPLY ONLY 5.5V FOR OTP
VOTP
AD5100
PROTECTION
For automotive applications, proper external protections on the AD5100 are needed to ensure reliable operation. The V1MON is likely to be used for battery monitoring. The V2MON is likely to be used for ignition switch or other critical inputs. As a result, these inputs may need additional protections such as EMI, load dump, and ESD protections. In addition, battery input requires reverse battery protection and short-circuit fuse protection (see Figure 20).
Load Dump Protection
A load dump is a severe overvoltage surge that occurs when the car battery is being disconnected from a spinning alternator and a resulting long duration, high voltage surge is introduced into the supply line. Therefore, external load dump protection is recommended. Typically, the load dump overvoltage lasts for a few hundred milliseconds and peaks at around 40 V to 70 V, while current can be as high as 1 A. As a result, a load dumprated TVS D1 and D2, such as SMCJ17, are used to handle the surge energy. A series resistor is an inline current limiting resistor; it should be adequate to limit the current without significant drop and yet small enough to not affect the input monitoring accuracy.
Overcurrent Protection
If the V1MON is shorted internally in the AD5100 to GND, the short-circuit protection kicks in and limits subsequent current to 150 mA in normal operation or 50 mA when the VOTP is executed.
Reverse Battery Protection
Reverse battery protection can be provided by a regular diode if the battery monitoring accuracy can be relaxed. Otherwise, a 60 V P-channel power MOSFET, like the NDT2955, can be used. Because of the MOSFET internal diode, the battery first conducts through the P1 body diode as soon as the voltage reaches its source terminal. The voltage divider provides adequate gateto-source voltage to turn on P1, and the voltage drop across the FET is negligible. The resistor divider values are chosen such that the maximum VGS of the P1 is not violated and the current drawn through the battery is only a few microamps.
Thermal Shutdown
When the AD5100 junction temperature is near the junction temperature limit, it automatically shuts down and cuts out the power from V1MON. The part resumes operation when the device junction temperature returns to normal.
ESD Protection
It is common to require a contact rating of 8 kV and a no contact or air rating of 15 kV ESD protection for the automotive electronics. As a result, an ESD-rated protection device must be used, such as MMBZ27VCL, a dual 40 W transient voltage suppressor (TVS) at the V1MON and V2MON.
EMI Protection
For EMI protection, a ferrite bead or EMC rated inductor, such as DR331-7-103, can be used.
VREG L1 10H C1 0.1F DR331-7-103 P1 NDT2955 R3 2.2 C3 10F R1 2M D1 V1MON EN VREF
R2 1.5M F1 B+ L1 - VMAIN IGNITION SWITCH C2 0.1F +
SMCJ17
DIGIPOT
AD5100
R4 2.2 D2 D3 D4 DIGIPOT V2MON
SMCJ17
MMBZ27VCL
Figure 20. Protection Circuits
Rev. 0 | Page 22 of 36
05692-020
AD5100 AD5100 REGISTER MAP
Table 11 outlines the AD5100 register map, used to configure and control all parameters and functions in the AD5100, and indicates whether registers are writable, readable, or permanently settable. All registers have the same address for read and write operations. The AD5100 ships from its manufacturing factory with default power-up values as listed in the last column. The user can experiment with different settings in the various threshold, delay, and configuration registers. Once evaluation is complete, the user's own power-up default values can be programmed via a one-time program (OTP) feature. When all desired settings have been programmed (or the user is satisfied with the manufacturer's defaults), a lock-out bit can be programmed (via OTP) to prevent further/erroneous settings from being programmed. The lockout bit is Register 0x15[3]. Some users may use the AD5100 as a set-and-forget device, that is, program some default values and never need to change these over the life of the application. However, some users may require on-the-fly flexibility, that is, the ability to change settings to values other than those they choose as their defaults. An additional feature of the AD5100 is the ability to temporarily override the OTP executed settings and still allow users to program the parts dynamically in the field. All override values revert to OTP-executed settings once the AD5100 is power cycled. Register writing, reading, OTP, and override are explained in the I2C Serial Interface section.
Table 11. AD5100 Register Map
Register Address 0x01 Read/ Write R/W Permanently Settable Yes Register Name and Bit Description V1MON overvoltage threshold Bit No. Description [3:0] Four bits used to program V1MON OV threshold [7:4] Reserved V1MON undervoltage threshold Bit No. Description [3:0] Four bits used to program V1MON UV threshold [7:4] Reserved V2MON turn-on threshold Bit No. Description [3:0] Four bits used to program V2MON on threshold [7:4] Reserved V2MON turn-off threshold Bit No. Description [3:0] Four bits used to program V2MON off threshold [7:4] Reserved V3MON RESET Threshold Bit No. Description [2:0] Three bits used to program V3MON RESET threshold [7:3] Reserved V4MON RESET threshold Bit No. Description [2:0] Three bits used to program V4MON RESET threshold [7:3] Reserved V1MON OV/UV triggered SHDN hold (t1SD_HOLD) Bit No. [2:0] [7:3] Description Three bits used to program V1MON OV/UV triggered SHDN hold time Reserved Pre-OTP Power-On Default 1 0x00 (18.00 V)
0x02
R/W
Yes
0x00 (8.43 V)
0x03
R/W
Yes
0x00 (7.47 V)
0x04
R/W
Yes
0x00 (6.95 V)
0x05
R/W
Yes
0x00 (2.93 V)
0x06
R/W
Yes
0x00 (7.54 V)
0x07
R/W
Yes
0x00 (200 ms)
Rev. 0 | Page 23 of 36
AD5100
Register Address 0x08 Read/ Write R/W Permanently Settable Yes Register Name and Bit Description V1MON OV/UV triggered SHDN delay (t1SD_DELAY) Description Three bits used to program V1MON OV/UV triggered SHDN delay time [7:3] Reserved V2MON turn-on triggered SHDN hold (t2SD_HOLD) Bit No. Description [2:0] Three bits used to program V2MON tON triggered SHDN hold time [7:3] Reserved V2MON turn-off triggered SHDN delay (t2SD_DELAY) Bit No. Description [2:0] Three bits used to program V2MON tOFF triggered SHDN delay time [7:3] Reserved RESET hold (tRS_HOLD) Bit No. Description [2:0] Three bits used to program RESET hold time [7:3] Reserved Watchdog timeout (tWD) Bit No. Description [2:0] Three bits used to program watchdog timeout time [7:3] Reserved RESET configuration Bit No. [0] Description 0: RESET is active when SHDN is active 1: RESET is not active when SHDN is active [1] 0: RESET active low 1: RESET active high [2] 0: enables V4MON under threshold, causing RESET 1: prevents V4MON under threshold from causing RESET (for V4OUT applications) [3] 0: floating WDI does not activate RESET 1: floating WDI activates RESET [7:4] Reserved SHDN rail voltage configuration Bit No. [2:0] [3] Description Reserved 0: SHDN rail = V1MON 1: SHDN rail = VREG 0x00 Bit No. [2:0] Pre-OTP Power-On Default 1 0x00 (1200 ms)
0x09
R/W
Yes
0x00 (10 ms)
0x0A
R/W
Yes
0x00 (100 ms)
0x0B
R/W
Yes
0x00 (200 ms)
0x0C
R/W
Yes
0x00 (1500 ms)
0x0D
R/W
Yes
0x00
0x0E
R/W
Yes
0x00
0x0F
R/W
Yes
[7:4] Reserved Watchdog mode Bit No. Description [2:0] Reserved [3] 0: standard mode 1: advanced mode [7:4] Reserved
Rev. 0 | Page 24 of 36
AD5100
Register Address 0x15 Read/ Write R/W Permanently Settable Yes Register Name and Bit Description Program lock (inhibit further programming) Bit No. Description [2:0] Reserved [3] 0: further fuse programming allowed 1: further fuse programming disabled (note that this bit is OTP only) [7:4] Reserved Special function 1 Bit No. Description [0] 0: OTP enables 5 A fuse readback sense current 1: OTP enables 0.55 A fuse readback sense current [1] 0: OTP disables blowing fuses 1: OTP enables blowing fuses [2] 0: software assertion of SHDN pin is inactive 1: pulls SHDN pin low [3] 0: override of permanent settings inactive 1: override of permanent settings active [7:4] Reserved Special function 2 Bit No. Description [0] 0: software power-down of AD5100 inactive 1: software power-down of AD5100 active 2 [7:1] Reserved Disable special functions 3 Bit No. Description [0] 0: allows override of any of the registers in memory except Register 0x16 Bit[2:0] and Register 0x17 Bit[0] 1: disables override of any of the registers in memory except Register 0x16 Bit[2:0] and Register 0x17 Bit[0] [1] 0: allows OTP function 1: disables OTP function [2] Reserved [3] 0: allows software power-down function 1: disables software power-down function [4] 0: allows software assertion of SHDN pin 1: disables software assertion of SHDN pin [7:5] Reserved Pre-OTP Power-On Default 1 0x00
0x16
R/W
No
0x00
0x17
R/W
No
0x00
0x18
R/W
No
0x00
Rev. 0 | Page 25 of 36
AD5100
Register Address 0x19 Read/ Write Readonly Permanently Settable No Register Name and Bit Description Fault detect and status (Bits[3:0] are level triggered bits that indicate the current state of the comparators monitoring the V1MON and V2MON input pins; Bits[6:4] are edge triggered fault detection bits that indicate what error conditions were present when a SHDN event occurred) Bit No. [0] [1] [2] [3] [6:4] Description 1 = V2MON input < V2MON off threshold 1 = V2MON input > V2MON on threshold 1 = V1MON input < V1MON UV threshold 1 = V1MON input > V1MON OV threshold 000: none 001: V1MON UV only 010: V1MON OV only 011: never occurred 100: V2MON below off only (default) 101: V1MON UV and V2MON below off both occurred 110: V1MON OV and V2MON below off both occurred 111: never occurred Reserved Pre-OTP Power-On Default 1 0x40
[7]
1 2
Default settings of AD5100 when shipped from manufacturer's factory. V2MON must be 0 V (that is, V2MON must be configured in edge sensitive mode) for software power-down. 3 These register bits are set only. To clear them, the AD5100 must be power cycled. In some cases, the AD5100 can be connected to an I2C bus with lots of activity. Setting these bits is an added means of ensuring that any erroneous activity on the bus does not cause AD5100 special functions to become active.
Rev. 0 | Page 26 of 36
AD5100 I2C SERIAL INTERFACE
Control of the AD5100 is accomplished via an I2C-compatible serial bus. The AD5100 is connected to this bus as a slave device (the AD5100 has no master capabilities). The 2-wire serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a start condition, which occurs when SDA goes from high to low while SCL is high. The following byte is the slave address byte, which consists of the 7-bit slave address followed by an R/W bit that determines whether data is read from or written to the slave device Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL. When all data bits have been read or written, a stop condition is established by the master. A stop condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition. In the read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the 10th clock pulse and high during the 10th clock pulse to establish a stop condition.
SCL
The serial input register clock pin shifts in one bit at a time on positive clock edges. An external 2.2 k to 10 k pull-up resistor is needed. The pull-up resistor should be tied to V3MON, provided V3MON is sub-5 V.
SDA
The serial data input/output pin shifts in one bit at a time on positive clock edges, with the MSB loaded first. An external 2.2 k to 10 k pull-up resistor is needed. The pull-up resistor should be tied to V3MON , provided V3MON is sub-5 V.
2.
AD0
The AD5100 has a 7-bit slave address. The six MSBs are 010111, and the LSB is determined by the state of the AD0 pin. When the I2C slave address pin, AD0, is low, the 7-bit AD5100 slave address is 0101110. When AD0 is high, the 7-bit AD5100 slave address is 0101111 (pulled up to 3.3 V maximum). The AD0 pin allows the user to connect two AD5100 devices to the same I2C bus . Table 13 and Figure 21 show an example of two AD5100 devices operating on the same serial bus independently. Table 13. Slave Address Decoding Scheme
AD0 Programming Bit 0 1 AD0 Device Pin 0V 3.3 V max Device Addressed 0x2E (U1) 0x2F (U2)
3.
For the AD5100, write operations contain either one or two bytes, while read operations contain one byte. The AD5100 makes use of an address pointer register. This address pointer sets up one of the other registers for the second byte of the write operation or for a subsequent read operation. Table 12 shows the structure of the address pointer register. Bits [6:0] signify the address of the register that is to be written to or read from. Bit 7 is used when OTP mode is invoked (use of this bit is explained in the One-Time Programmable (OTP) Options section) and should be 0 for normal write/read operations. Table 12. Address Pointer Register Structure
Bit Number 7 6 5 4 3 2 1 0 Function OTP enable Address Bit 6 Address Bit 5 Address Bit 4 Address Bit 3 Address Bit 2 Address Bit 1 Address Bit 0 (LSB)
5V Rp Rp
SDA MASTER SCL SDA SCL AD0 3.3V MAX
5V
SDA SCL AD0
05692-021
AD5100
U1
AD5100
U2
Figure 21. Two AD5100 Devices on One Bus
Rev. 0 | Page 27 of 36
AD5100
WRITING DATA TO AD5100
When writing data to the AD5100, the user begins by writing an address byte followed by the R/W bit set to 0. The AD5100 acknowledges (if the correct address byte is used) by pulling the SDA line low during the ninth clock pulse. The user then follows with two data bytes. The first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. The second byte is the data to be written to the internal data register. After each byte, the AD5100 acknowledges by pulling the SDA line low during the ninth clock pulse. Figure 22 illustrates this operation. * If the address pointer is known to be already at the desired address, data can be read from the corresponding data register without first writing to the address pointer register.
Table 14 shows the readback data byte structure. Bits[6:0] contain the data from the register just read. Bit 7 only has significance when OTP mode is being used, and should be ignored for normal read operations. The majority of AD5100 registers are four bits wide, with only the fault detect and status register and disable special functions register at seven bits and five bits wide, respectively. Table 14. Readback Data Byte Structure
Bit Number 7 6 5 4 3 2 1 0 Function OTP Okay D6 D5 D4 D3 D2 D1 D0 (LSB)
READING DATA FROM AD5100
When reading data from an AD5100 register, there are two possibilities. * If the AD5100 address pointer register value is unknown or not at the desired value, it is first necessary to set it to the correct value before data can be read from the desired data register. This is done by performing a write to the AD5100, but only a value containing the register address is sent because data is not to be written to the register. This is shown in Figure 23. A read operation is then performed consisting of the serial bus address, R/W bit set to 1, followed by the data byte from the data register. This is shown in Figure 24.
SCL SDA 0 1 0 1 1 1 AD0 R/W
OTP AP6 AP5 AP4 AP3 AP2 AP1 AP0
D7 ACK. BY AD5100
D6
D5
D4
D3
D2
D1
D0 ACK. BY AD5100
ACK. BY AD5100 START BY MASTER FRAME 1 SLAVE ADDRESS BYTE FRAME 2 ADDRESS POINTER BYTE
FRAME 3 DATA BYTE
STOP BY MASTER
Figure 22. Writing a Register Address to the Address Pointer Register, Then Writing Data to the Selected Register
SCL SDA 0 1 0 1 1 1 AD0 R/W OTP AP6 AP5 AP4 AP3 AP2 AP1 AP0 ACK. BY AD5100 FRAME 2 ADDRESS POINTER BYTE STOP BY MASTER
05692-023
ACK. BY AD5100 START BY MASTER FRAME 1 SLAVE ADDRESS BYTE
Figure 23. Dummy Write to Set Proper Address Pointer
SCL SDA 0 1 0 1 1 1 AD0 R/W OTP D6 OK ACK. BY AD5100 D5 D4 D3 D2 D1 D0 NO ACK. BY MASTER STOP BY MASTER
START BY MASTER
FRAME 1 SLAVE ADDRESS BYTE
FRAME 2 READ DATA BYTE
Figure 24. Read Data from the Address Pointer Register
Rev. 0 | Page 28 of 36
05692-024
05692-022
AD5100
PERMANENT SETTING OF AD5100 REGISTERS (OTP FUNCTION)
When the user wants to permanently program settings to the AD5100, the one-time program (OTP) function is invoked (note the requirements for the capacitor on the VOTP pin in the Power Requirements section). To complete a permanent program cycle for a particular register, the following sequence should be used: 1. 2. 3. 4. Set Bit 0 = 1 in Register 0x16 using a normal write operation. Set Bit 1 = 1 in Register 0x16 using a normal write operation. Apply a 5.5 V (100 mA) voltage source to the OTP pin. This provides the current for the programming cycle. Write the desired permanent data to the register of choice, using a write operation with the OTP bit set to 1 in the address pointer byte. Wait a period of 12 ms for the AD5100 to perform the permanent setting of the internal register. reading back and verifying the V1MON overvoltage threshold register (assuming that Step 1 to Step 3 have already been completed). When all default registers have been programmed, the lock bit should be set. User-programmed defaults do not become active until the lock bit is programmed. Programming the lock bit is done in exactly the same manner as all other registers in Table 11. The lock bit is Register 0x15, Bit 3.
TEMPORARY OVERRIDE OF DEFAULT SETTINGS
Even with the lock bit set, it is possible to temporarily override the default values of any of the permanently programmable registers. To override a permanent setting in a particular register (when the lock bit is programmed), the following sequence should be used: 1. 2. Set Bit 3 = 1 in Register 0x16 (special function 1). Write the desired temporary data to the register of choice.
5.
While the override bit (Bit 3) is set in Register 0x16, the user can override any registers by simply writing to them with new data. To reset an overridden register to its default setting, the following sequence should be used: 1. 2. Set Bit 3 = 0 in Register 0x16. Write a dummy byte to the register of choice.
The user has the opportunity to check whether the AD5100 is programmed correctly by performing a read instruction with the OTP bit set to 1 in the address pointer byte (for example, set the address pointer to 0x81 to check V1MON-OV) and monitoring the state of Bit 7 (OTP okay) in the read back data byte. * * OTP okay = 1 indicates that the AD5100 is programmed correctly OTP okay = 0 indicates that the AD5100 is programmed incorrectly
Note that read back of the OTP okay bit is available only for the read cycle following immediately after the program cycle. If a write or read of a different register is done immediately after the program cycle, the opportunity for verifying whether the programming was successful will have been missed. Figure 25 shows the recommended way of executing a program, then
12ms DELAY
Clearing the override bit in Register 0x16 does not cause all overridden registers to revert to their defaults at the same time. For example, imagine that the user overrides Register 0x01, Register 0x02, and Register 0x03. If the user subsequently clears the override bit in Register 0x16 and writes a dummy byte to Register 0x01, Register 0x01 reverts to its default value. However, Register 0x02 and Register 0x03 still contain their override data. To revert both registers to their default values, the user must write dummy data to each register individually. Power cycling the AD5100 also resets all registers to their programmed defaults.
S 010111AD0 DEVICE ADDRESS
W ACK
0x81 SET ADDR POINTER TO V1MON OVTHRES OTP BIT =1
ACK
0x0F SET V1MON OV THRESHOLD = 13.2V
ACK P
S
010111AD0 DEVICE ADDRESS
R ACK
0x81 SET ADDR POINTER TO V1MON OV THRES OTP BIT =1
ACK
0x8F CONFIRMED V1MON OV THRESHOLD = 13.2V
NACK
P
OUTPUT FROM MASTER OUTPUT FROM AD5100
S = START BIT P = STOP BIT
ACK =ACKNOWLEDGE NACK = NO ACKNOWLEDGE
R = READ W = WRITE
05692-125
Figure 25. Setting and Validating OTP Register Setting
Rev. 0 | Page 29 of 36
AD5100 APPLICATIONS INFORMATION
CAR BATTERY AND INFOTAINMENT SYSTEM SUPPLY MONITORING
The AD5100 has two high voltage monitoring inputs with shutdown and reset controls over external devices. For example, the V1MON and V2MON can be used to monitor the signals from a car battery and an ignition key in an automobile, respectively (see Figure 26). The shutdown output can be connected to the shutdown pin of an external regulator to prevent false conditions such as a weak battery or overcharging of a battery by an alternator. The reset output can be used to reset the processor in the event of a hardware or software malfunction. An example of the input and output responses of this circuit is shown in Figure 27.
Rev. 0 | Page 30 of 36
VREG VREG EN R3 2.2 C3 10F D1 OV FD SMCJ17 DIGIPOT UV FD V2MON D2 ON DIGIPOT 12C SHDN FD OFF DAC DIGIPOT 1 2 RESET 3 DRIVER D3 D4 PROGRAMMABLE DRIVER LOAD DESELECT SHDN V1MON R1 2M R2 1.5M R4 2.2 VREF OSC
AD5100
L1 10H
NDT2955
C1 0.1F
DR331-7-103
P1
VIN VOUT VREG1 SD GND
+5V
F1
B+
L1
IGNITION SWITCH
-
+
VMAIN
C2 0.1F
SHUTDOWN CONTROLLER AND ADJUSTABLE SHDN HOLD AND DELAY
VIN VOUT VREG2 SD VCC PA GND
+3.3
SMCJ17 V3MON
MMBZ27VCL
05692-025
Figure 26. Typical DSP in Car Infotainment Application
V4MON DIGIPOT V3MON RESET GENERATOR AND ADJUSTABLE RESET HOLD MR WDI VOTP C2 10F V3MON OTP FUSE ARRAY R2 SCL SDA DAC AD0 R3 I2C CONTROLLER I2C SHDN MEMORY MAP C3 0.1F PROGRAMMABLE WATCHDOG 4 TIMES RESET GENERATOR FD REGISTER (FAULT DETECTION)
Rev. 0 | Page 31 of 36
V4OUT
1.8V
VDD
I/O
DSP/ MICROPROCESSOR
3.3V
DVDD
I/O
RESET
SIGNAL
CODEC
SET CONFIGURATIONS PROGRAM PARAMETERS READ STATUS
SHDNWARN
IN
OUT
AD5100
AD5100
OV UV BATTERY < tGLITCH
IGNITION
VREG
tVREG_ON_DELAY
UV SHUTDOWN
tVREG_OFF_DELAY
MICROPROCESSOR FAILED SHUTDOWN V2MON OFF SHUTDOWN
SHDN
5V
3.3V
WDI
MR SHUTDOWN ENABLE RESET +5V BROWNOUT RESET MICROPROCESSOR FAILED RESET HIGH-Z WDI RESET SHUTDOWN ENABLE RESET
05692-026
RESET
HIGH-Z
WDI RESET
MR RESET
Figure 27. Example of SHDN and RESET Responses of Circuit Shown in Figure 26
Rev. 0 | Page 32 of 36
AD5100
BATTERY MONITORING WITH FAN CONTROL
V4MON can be used with V4OUT in tandem to form a simple PWM control circuit. For example, as shown in Figure 28, when a temperature sensor output connects to the V4MON input, with the proper threshold level set, V4OUT outputs high whenever the temperature goes above the threshold. This turns on the FET switch, which activates the fan. When VTEMP drops below the threshold, V4OUT decreases, which turns off the fan.
BATTERY STATE OF CHARGE INDICATOR AND SHUTDOWN EARLY WARNING MONITORING
In the automotive application, the system designer may set the battery threshold to the lowest level to allow an automobile to start at the worst-case condition. If the battery remains at the low voltage level, it is indeed a poor battery. However, there is no way to warn the driver. As a result, the system designer can use V4OUT as the battery warning indicator. By stepping down the battery voltage monitored at V4MON, the LED is lit, which gives a battery replacement warning. The circuit is shown in Figure 30.
VTEMP TMP35
BATTERY
VREG SD
VREG
PA
BATTERY IGNITION VREG VTEMP MR WDI
V1MON V2MON V3MON V4MON MR WDI SCL SDA
SHDN
AD5100
V4OUT
RESET SHDNWARN
MICROPROCESSOR
MR WDI
CLK
MISO/MOSI
CLK
Figure 28. Power Amp Monitoring and Fan Control
VTEMP V4MON THRESHOLD
V4OUT
05692-027
NOTES 1. V4MON RESET DISABLED.
Figure 29. V4OUT with Respect to VTEMP, with V4MON RESET Disabled in Circuit Shown in Figure 28
IGNITION BATTERY
V2MON V1MON
SHDN
AD5100
V4MON V4OUT
MICROPROCESSOR SCL SDA SHDNWARN CLK MISO/MOSI
CLK
Figure 30. Battery State of Charge Indication
Rev. 0 | Page 33 of 36
05692-029
05692-028
AD5100
RISING EDGE TRIGGERED WAKE-UP MODE
As indicated in Figure 31, the microprocessor can control its own power-down sequence using the rising edge triggered wake-up signal. The operator must select the rising edge triggered wake-up mode setting for the V2MON turn-off threshold value, as shown in Table 6, by setting Register 0x04[3:1] = 1001. When the rising edge wake-up signal is detected by V2MON, the AD5100 is powered up with the SHDN pin pulled high. The external regulator is turned on to supply power to the microprocessor. A reset pulse train is generated at the reset output if there is no watchdog activity. The pulse continues until the correct watchdog signal appears at the AD5100 WDI pin. The shutdown pin remains high as long as the AD5100 continues to receive the correct watchdog signal. When the microprocessor finishes its housekeeping tasks or powers down the software routine, it stops sending a watchdog signal. In response, the AD5100 generates a reset. The shutdown pin is pulled low 2 seconds after, and the regulator output drops to 0 V, which shuts down the microprocessor. At that point, the AD5100 enters sleep mode.
VI
VO VREG
BATTERY CAN WAKE UP PULSE(S)
V1MON V2MON
SHDN
SD
AD5100
VDD
I/O
SCL SDA WDI RESET
MICROPROCESSOR I/O RS I/O
Figure 31. Rising Edge Triggered Wake-Up Mode
V2MON
WDI
RESET
SCL
SCL
SDA
SDA WRITE
SHDN
NOTES 1. 6V < V1MON < 30V. 2. SELECT V2MON_OFF = RISING EDGE TRIGGER/CAN WAKE UP MODE.
05692-030
Figure 32. Rising Edge Triggered Operation of Circuit Shown in Figure 31
Rev. 0 | Page 34 of 36
05692-031
AD5100 OUTLINE DIMENSIONS
0.197 (5.00) 0.193 (4.90) 0.189 (4.80)
16
9
1
0.158 (4.01) 0.154 (3.91) 0.150 (3.81)
8
0.244 (6.20) 0.236 (5.99) 0.228 (5.79)
0.065 (1.65) 0.049 (1.25) 0.010 (0.25) 0.004 (0.10) COPLANARITY 0.004 (0.10)
0.069 (1.75) 0.053 (1.35) SEATING PLANE 0.012 (0.30) 0.008 (0.20) 8 0
0.010 (0.25) 0.006 (0.15)
0.020 (0.51) 0.010 (0.25)
0.025 (0.64) BSC
0.050 (1.27) 0.016 (0.41)
0.041 (1.04) REF
COMPLIANT TO JEDEC STANDARDS MO-137-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012808-A
Figure 33. 16-Lead Shrink Small Outline Package [QSOP] (RQ-16) Dimensions shown in inches
ORDERING GUIDE
Model AD5100YRQZ-RL7 1 AD5100YRQZ1
1
Temperature Range -40C to +125C -40C to +125C
Package Description 16-Lead QSOP 16-Lead QSOP
Package Option RQ-16 RQ-16
Ordering Quantity 1,000 9,800
Z = RoHS Compliant Part.
Rev. 0 | Page 35 of 36
AD5100 NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05692-0-9/08(0)
Rev. 0 | Page 36 of 36

▲Up To Search▲

Price & Availability of AD5100

	To Download AD5100 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .